1. Field of Invention
The techniques described herein relate generally to transistor switches, and more specifically to analog switches.
2. Discussion of the Related Art
Analog switches are commonly used circuit components that can provide great design flexibility at the system level. Various types of analog switches have been used.
FIG. 1A shows a first type of analog switch 10 that includes an NMOS transistor 1 and a PMOS transistor 2 in parallel between the input and output terminals of the analog switch 10. The input terminal of analog switch 10 is connected to the source terminal of the NMOS transistor 1 and the drain terminal of the PMOS transistor 2. The drain terminal of the NMOS transistor 1 and the source terminal of the PMOS transistor 2 are connected to the output terminal of the analog switch 10. The analog switch 10 is formed in a semiconductor substrate. The region of the substrate in which NMOS transistor 1 is formed is biased at ground voltage. The region of the substrate in which PMOS transistor 2 is formed is biased at voltage VDD. The configuration of analog switch 10 having parallel NMOS and PMOS transistors will be referred to herein as an “elemental analog switch.” More complex analog switches can be formed using the elemental analog switch.
The gate 3 of the NMOS transistor 1 is driven by the NMOS gate control signal NG_CTL. The gate 4 of the PMOS transistor 2 is driven by the PMOS gate control signal PG_CTL. When the control signal NG_CTL is at voltage VDD and the control signal PG_CTL is at ground voltage, the analog switch 10 is turned on, and current can flow through the analog switch 10 between the input and output terminals. When the NMOS gate control signal NG_CTL is at a ground voltage and the PMOS gate control signal PG_CTL is at voltage VDD, the analog switch is turned off. The gate control signals NG_CTL and PG_CTL are complementary, such that control signal NG_CTL is at a low voltage level when control signal PG_CTL is at a high voltage level, and the control signal NG_CTL is at a high voltage level when the control signal PG_CTL is at a low voltage level. The NMOS transistor 1 is turned on when the control signal NG_CTL is at a high voltage level, allowing current to flow through the NMOS transistor between its source and drain terminals. The PMOS transistor 2 is turned on when the control signal PG_CTL is at a low voltage level, allowing current to flow through the PMOS transistor 2 between its source and drain terminals. Applying complementary control signals NG_CTL and PG_CTL to the gates of transistors 1 and 2 causes the transistors to be turned on at the same time and turned off at the same time. When the analog switch is in the on state, both NMOS transistor 1 and PMOS transistor 2 are turned on, allowing current to flow between the input and output terminals. When the analog switch is in the off state, both the NMOS transistor 1 and the PMOS transistor 2 are turned off, substantially preventing a signal from flowing between the input and output terminals of the analog switch. The presence of parasitic signal paths between the input and output terminals of the analog switch 10 does not allow the output terminal to be completely isolated from the input terminal when the analog switch 10 is in the off state. As a consequence, some of the signal present at the input terminal is coupled to the output terminal when the analog switch 10 is in the off state.
FIG. 1B shows the equivalent circuit 11 of the analog switch 10 when the analog switch 10 is in the off state. The equivalent circuit 11 is a high pass filter that includes a resistance R1 in parallel with a capacitor C1. R1 represents the resistance of the analog switch 10 in the off state, which can be in the range of megaohms or hundreds of kiloohms. C1 represents the capacitive coupling between the input and output nodes through parasitic signal paths. Due to the capacitive coupling, high frequency signals can propagate from the input terminal to the output terminal when the analog switch 10 is in the off state. The off state isolation for the analog switch 10 for a 1 MHz signal is about 45 dB.
There are five parasitic signal paths through analog switch 10 that couple the input terminal to the output terminal when the analog switch 10 is in the off state. The first path is through a parasitic capacitance between the input terminal and the gate 3 of the NMOS transistor 1, and through the parasitic capacitance between gate 3 and the output terminal. FIG. 2A shows the equivalent circuit for this first path, which includes the two parasitic capacitances and a shunt resistance Rp1 to ground. Rp1 is the on-resistance of the control circuit (not shown) that generates the NMOS gate control signal NG_CTL. The second path is through the parasitic capacitance between the input terminal and the region of the substrate 5 in which the NMOS transistor 1 is formed, and through the parasitic capacitance between this region of the substrate 5 and the output terminal. FIG. 2B shows the equivalent circuit for the second path, which includes two parasitic capacitances and a shunt resistance Rp2 to ground. Rp2 is the resistance through the NMOS bulk substrate region and the metal connection to ground. The third path is through the parasitic capacitance between the input terminal and the gate 4 of the PMOS transistor 2, and through the parasitic capacitance between gate 4 and the output terminal. FIG. 2C shows the equivalent circuit for the third path, which includes two parasitic capacitances and a shunt resistance Rp3 to VDD. Rp3 is the on-resistance of the control circuit (not shown) that generates the PMOS gate control signal PG_CTL. The fourth path is through the parasitic capacitance between the input terminal and the region of the substrate 6 in which the PMOS transistor 2 is formed, and through the parasitic capacitance between this region of the substrate 6 and the output terminal. FIG. 2D shows the equivalent circuit for the fourth path, which includes two parasitic capacitances and a shunt resistance Rp4 to VDD. Rp3 is the resistance through the PMOS bulk substrate region and the metal connection to terminal VDD. The fifth path is through the source-drain parasitic capacitances of the NMOS transistor 1 and the PMOS transistor 2. The fifth path is actually two separate paths: a path from the input terminal and the source terminal of the NMOS transistor 1 through the parasitic source-drain capacitance of the NMOS transistor 1 to the output terminal; and another path from the input terminal and the drain terminal of the PMOS transistor 2 through the parasitic source-drain capacitance of the PMOS transistor 2 to the output terminal. FIG. 2E shows the equivalent circuit for the fifth path, which is represented as a single capacitor representing the parallel combination of these paths through both the NMOS and PMOS transistors. These five parasitic signal paths allow coupling of the signal from the input terminal to the output terminal when the analog switch 10 is in the off state.
FIG. 3 shows another type of analog switch known as a T switch. T switch 30 includes two of the elemental analog switches 10 connected in series. T switch 30 includes an NMOS transistor 31 in parallel with a PMOS transistor 32 and an NMOS transistor 33 in parallel with a PMOS transistor 34. NMOS transistor 31 is in series with NMOS transistor 33 between the input and output terminals of the T switch 30. PMOS transistor 32 is in series with PMOS transistor 34 between the input and output terminals of the T switch 30. The connection points between NMOS transistors 31 and 33 and PMOS transistors 32 and 34 are connected to each other and to an NMOS shunt transistor 35 that is connected to ground. The gates of the NMOS transistors 31 and 33 are driven by NMOS gate control signal NG_CTL and the gates of the PMOS transistors 32 and 34 are driven by PMOS gate control signal PG_CTL. The NMOS shunt transistor is also driven by control signal PG_CTL.
The T switch 30 has improved off state isolation compared to the elemental analog switch shown in FIG. 1A. When the T switch 30 is in the off state, the transistors 31-34 are turned off and the NMOS shunt transistor 35 is turned on. Turning on NMOS shunt transistor 35 couples the connection point of transistors 31-34 to ground, thereby shunting parasitic signals from the input terminal away from the output terminal of the T switch. The NMOS shunt transistor 35 can reduce the effects of the fifth parasitic signal path by coupling the connection point of transistors 31-34 to ground. In addition, NMOS transistors 31 and 33 are formed in regions of the substrate that have separate connections to ground, which reduces coupling through the second parasitic path. Similarly, PMOS transistors 32 and 34 are formed in regions of the substrate that have separate connections to VDD, which reduces coupling through the fourth parasitic path. These reductions in parasitic coupling provide improved off state isolation compared to the elemental analog switch. For example, the off state isolation of the T switch 30 for a 1 MHz signal can be 60 dB. One problem with T switch 30 is that it can have reduced linearity in the on state.
FIG. 4 shows a T switch 40 having a substrate voltage control circuit 41 that can improve the linearity of the T switch. When the T switch 40 is in the on state, the substrate voltage control circuit 41 controls the voltage of the regions of the substrate in which PMOS transistors 32 and 34 are located. The voltage of these regions is controlled based on the input signal applied to the input terminal of T switch 40.
The substrate voltage control circuit 41 includes two elemental analog switches in series between the input and output terminals of the T switch 40. Substrate voltage control circuit 41 includes an NMOS transistor 42 in parallel with a PMOS transistor 43 and an NMOS transistor 44 in parallel with a PMOS transistor 45. NMOS transistor 42 is in series with NMOS transistor 44 between the input and output terminals of the T switch 40. PMOS transistor 43 is in series with PMOS transistor 45 between the input and output terminals of the T switch 40. The NMOS transistors 42 and 44 and PMOS transistors 43 and 45 are connected to each other and to a PMOS shunt transistor 46, which is connected to voltage VDD. The regions of the substrate in which NMOS transistors 42 and 44 are formed are biased at ground voltage. The regions of the substrate in which PMOS transistors 43 and 45 are formed are biased at voltage VDD. NMOS transistors 42 and 44 are driven by control signal NG_CTL and PMOS transistors 43 and 45 are driven by control signal PG_CTL. PMOS shunt transistor 46 is driven by control signal NG_CTL.
When the T switch 40 is in the on state, transistors 42-45 are turned on and PMOS shunt transistor 46 is turned off. The input signal flows through transistors 42-45. At the connection node of transistors 42-45, the input signal is applied to the regions of the substrate in which PMOS transistors 32 and 34 are formed, to improve linearity. When the T switch 40 is in the off state, transistors 42-45 and 31-34 are turned off, and transistor 46 is turned on. The connection point of transistors 42-45 and substrate regions of PMOS transistors 32 and 34 are coupled to voltage VDD through PMOS shunt transistor 46.
A problem with T switch 40 is that substrate voltage control circuit 41 reduces the isolation of the T switch in the off state. Substrate voltage control circuit 41 increases the parasitic coupling between the input and output terminals.